Capacitor for semiconductor device and fabricating method thereof

ABSTRACT

A capacitor for a semiconductor device includes a first inter metal dielectric layer is disposed on a substrate. A first electrode is disposed on the first inter metal dielectric layer. A second electrode partially overlaps the first electrode. A first dielectric layer is disposed between the first and second electrodes. A third electrode partially overlaps the second electrode. A second dielectric layer is disposed between the second and third electrodes. An etch stop layer is disposed on the first, second, and third electrodes. A second inter metal dielectric layer is formed on the etch stop layer and includes first, second, and third via holes exposing the first and third electrodes and the etch stop layer. First, second, and third plugs are disposed in the first, second, and third via holes.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a semiconductor device and, moreparticularly, to a capacitor having metal/insulator/metal (MIM)structure and a method for fabricating the capacitor.

(b) Description of the Related Art

An MIM capacitor for a semiconductor device is formed as ametal/insulator/metal structure. The metal and insulator structures arelayered on one another, such that a required capacitance can beprovided.

Metal wirings are formed on an inter metal dielectric of the capacitor,and the metal wirings are connected to electrodes through plugs formedin the inter metal dielectric. By this arrangement, electricity can beapplied to the electrodes.

The layered structures include via holes defining the plugs, the viaholes having depths different from one another.

That is, the via holes are formed at different depths because theelectrodes are formed on different layers. Since the via holes areformed at different depths, the etch process is performed with respectto the deepest via hole, such that the surface of the electrodes (upperelectrode) exposed through the previously completed via holes aredamaged while etching the via hole for exposing the low part (lowerelectrode).

Such damage deteriorates characteristics of the semiconductor device,and reduces the reliability of the device. Accordingly, in order toreduce the damage to the electrodes the etching process is performedusing different masks according to the depths of the respective viaholes to be formed. However, the utilization of additional maskscomplicates the fabrication process and increase manufacturing costs.

SUMMARY OF THE INVENTION

To address the above-described and other problems, it is an object ofthe present invention to provide a capacitor for a semiconductor device.A first inter metal dielectric layer is disposed on a substrate. A firstelectrode is disposed on the first inter metal dielectric layer. Asecond electrode partially overlaps the first electrode. A firstdielectric layer is disposed between the first and second electrodes. Athird electrode partially overlaps the second electrode. A seconddielectric layer is disposed between the second and third electrodes. Anetch stop layer is disposed on the first, second, and third electrodes.A second inter metal dielectric layer is formed on the etch stop layerand includes first, second, and third via holes exposing the first andthird electrodes and the etch stop layer. First, second, and third plugsare disposed in the first, second, and third via holes.

The present invention further provides a method for fabricating acapacitor for a semiconductor device. A first inter metal dielectriclayer is formed on a substrate. A first metal layer is formed to fill atrench on the first inter metal dielectric layer. The first metal layeris polished using a chemical mechanical polishing to form a firstelectrode. A first dielectric layer, a second metal layer, a seconddielectric layer, and a third metal layer are formed on the firstelectrode. The third metal layer is patterned using a selective etchingto form a third electrode. The second metal layer is patterned using theselective etching to form a second electrode that overlaps the firstelectrode and the third electrode. An etch stop layer and a second intermetal dielectric layer are formed to cover the first, second, and thirdelectrodes. The second inter metal dielectric layer are etched using aselective photolithography process to form via holes to expose the etchstop layer. The etch stop layer is removed to expose the first, second,and third electrodes. The via holes are filled to form plugs, the plugselectric connecting with the first, second, and third electrodes. Metalwirings are formed on the second inter metal dielectric layer to conductelectricity to the first to third electrodes through the plugs.

The present invention still further provides a capacitor for asemiconductor device. A first dielectric layer is disposed on asubstrate. A first electrode is disposed on the first dielectric layer.A second electrode partially overlaps the first electrode. A seconddielectric layer is disposed between the first and second electrodes. Athird electrode partially overlaps the second electrode. A thirddielectric layer is disposed between the second and third electrodes. Anetch stop layer is disposed on the first, second, and third electrodes.A fourth dielectric layer is formed on the etch stop layer and includesfirst, second, and third via holes exposing the first and thirdelectrodes and the etch stop layer. First, second, and third plugsdisposed in the first, second, and third via holes.

It is to be understood that both the foregoing general description ofthe invention and the following detailed description are exemplary, butare not restrictive of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate an embodiment of the invention,and, together with the description, serve to explain the principles ofthe invention:

FIG. 1 is a cross sectional view illustrating a capacitor structure of asemiconductor device according to the present invention.

FIGS. 2-6 are cross sectional views illustrating fabrication steps forthe semiconductor device of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

With reference to the accompanying drawings, the present invention isdescribed. It is to be understood, however, that the scope of the claimsis not limited to the disclosed embodiments, but rather that variousmodifications and equivalent arrangements are included within the spiritand scope of the claims.

To clarify multiple layers and regions, the thickness of the layers areenlarged in the drawings. The same reference numbers are used throughoutthe drawings to refer to the same or similar parts.

FIG. 1 is a cross sectional view illustrating a capacitor structure of asemiconductor device according to the present invention.

As shown in FIG. 1, a first inter metal dielectric (or dielectric layer)10 is formed on a substrate 1. The substrate 1 includes semiconductordevices (not shown) and/or metal wirings (not shown). A first electrode12 is disposed in a trench formed in the first inter metal dielectric10.

On the first electrode 12, a first dielectric layer 14, a secondelectrode 16, a second dielectric layer 18, and a third electrode 20.The first dielectric layer 14 is arranged between the first electrode 12and the second electrode 16, and the second dielectric layer 18 isarranged between the second electrode 16 and the third electrode 20.Preferably, the first electrode 12, a first dielectric layer 14, asecond electrode 16, a second dielectric layer 18 are sequentiallydeposited.

The first to third electrodes 12, 16, and 20, and the first and seconddielectric layer 14 and 18 are covered by an etch stop layer 22 and aninter metal dielectric layer 24. Via holes are formed over the intermetal dielectric layer 24 and the etch stop layer 22 to expose the firstto third electrodes 12, 16, and 20. Specifically, a first via hole V1exposes the second electrode 18, a second via hole V2 exposes the thirdelectrode 20, and a third via hole V3 exposes the first electrode 12.

At least a portion of the first dielectric layer 14 between the firstelectrode 12 and the second electrode 16 and at least a portion of thesecond dielectric layer 18 are formed thicker than other portions. Thisfacilitates removal of portions of the dielectric layers 14 and 18, asdescribed below. The fabrication method is now described.

The first to third electrodes 12, 16, and 20 can be formed of copper,titanium/titanium nitride, aluminum, and/or tungsten. The dielectriclayers 14 and 18 can be formed of silicon nitride, silicon oxide,multiple layers including these materials, and/or one or more layersincluding high permittivity materials such as tantalum oxide.

An etch stop layer 22 and a second inter metal dielectric layer 24 areformed on the third electrode 20. The second inter metal dielectriclayer 24 and the etch stop layer 22 are provided with a first to thirdvia holes V1-V3 exposing the first, second, and third electrodes 12, 16,and 20, respectively. Inside the via holes V1-V3, plugs 26 and 28 areformed for connecting to the upper metal wirings. The plug 26 includes abarrier metal layer 26 formed along inner wall of the via holes V1-V3,and a layer 28 fills the via hole defined by the barrier metal layer 26.The layer 28 preferably is formed from tungsten.

On the second inter metal dielectric layer 24, metal wirings 30 connectto the first, second, and third electrodes 12, 16, and 20 through theplugs 26 and 28.

A method for fabricating the above described capacitor for thesemiconductor is now described with reference to FIGS. 2-6, which arecross sectional views illustrating fabrication steps.

As shown in FIG. 2, the first inter metal dielectric layer 10 is formedon the substrate 1, the substrate 1 including semiconductor devicesand/or the metal wirings.

The first inter metal dielectric layer 10 can be formed from a lowpermittivity material, such as plasma enhanced tetra ethyl orthosilicate (PE-TEOS), un-doped silicate glass (USG), and/or fluorinesilicate glass (FSG).

A trench is formed by etching a predetermined region of the first intermetal dielectric layer 10 through a selective etch process. The firstelectrode 12 is completed by forming the first metal layer by depositingcopper, titanium/titanium nitride, aluminum, and/or tungsten, andpolishing the metal layer through a chemical mechanical polishingprocess until the first inter metal dielectric layer 10 is exposed.

As shown in FIG. 3, the first dielectric layer 14, the second metallayer 16A, the second dielectric layer 18A, and a third metal layer aredeposited. Preferably, the first dielectric layer 14, the second metallayer 16A, the second dielectric layer 18A are sequentially deposited.The first dielectric layer 14 can be formed by depositing the siliconnitride and/or the silicon oxide in single or multiple layeredstructure, and/or can be formed having a layer made from a highpermittivity material such as tantalum oxide.

The third electrode 20 is formed by forming a photoresist pattern (PR1)on the third metal layer and etching the third metal layer using thephotoresist pattern (PR1) as an etching mask. The third electrode 20 isformed so as to partially overlap the first electrode 12.

At this time, the second dielectric layer 18A is etched so as to beformed at a thickness of about 100 Å. When the second dielectric layer18A is completely removed, the surface of the second metal layer 16A canbe damaged by the etchant or the etching gas in the following process,and thus it is preferable to leave at least a portion of the seconddielectric layer 18A.

As shown in FIG. 4, the second photoresist pattern (PR2) is formed onthe substrate 1. The second photoresist pattern (PR2) covers the thirdelectrode 20, and defines the second electrode 16. The second dielectriclayer 18 and the second electrode 16 are formed by etching the seconddielectric layer 18A and the second metal layer 16A using the secondphotoresist pattern (PR2) as a mask. The second photoresist pattern(PR2) can partially overlap the first electrode 12 while coveringsubstantially an entirety of the third electrode 20, such that the thirdelectrode 20 and the first electrode 12 are largely overlapped to formthe second electrode 16.

As shown in FIG. 5, the etch stop 22 and the second inter metaldielectric layer 24 can be formed on substantially an entire surface ofthe substrate. The etch stop layer 22 can be made from a material havinghigh etching selectivity to the second inter metal dielectric layer 24.

The second inter metal dielectric layer 24 can be formed from a materialidentical or similar to the first inter metal dielectric 10. When thesecond inter metal dielectric layer 24 is formed from an oxide material,the etch stop layer 22 is preferably formed from a nitride materialhaving high etching selectivity to the oxide material. A predeterminedregion of the second inter metal dielectric layer 24 is etched to theetch stop layer 22. Etching the etch stop layer 22 forms the first tothird via holes V1-V3 exposing the first, second, and third electrodes12, 16, and 20.

The via holes V1-V3 are formed to expose the respective electrode 12,16, and 20 after forming the etch stop layer 22 from the dielectricmaterial having high etching selectivity to the second inter metaldielectric 24, and thus the electrodes 12, 16, and 20 are not otherwiseexposed to the etching conditions, even thought the via holes V1-V3differ in depth. Thus, by this arrangement, it is possible to avoiddamage of the electrodes 12, 16, and 20.

Specifically, because of the high etching selectivity between the etchstop layer 22 and the second dielectric layer 24, the etch stop layer 22is not removed while removing the second inter metal dielectric layer24. Also, since there is little difference in thickness between the etchstop layer 22 and the respective electrodes 12, 16, and 20, the surfacesof the respective electrodes 12, 16, and 20 are not damaged duringremoval of the dielectric layer remaining after the etch stop layer 22is removed. Accordingly, the via holes V1-V3 can be completely formedwithout damaging the electrodes by performing the etching process duringa time period during which the electrodes are exposed.

As shown in FIG. 6, a barrier metal layer 26A is formed on the substrateand along the inner walls of the via holes. A layer 28A is filled in thevia holes V1-V3 coated by the barrier metal layer 26A. Preferably, thelayer 28A is formed from tungsten.

A chemical mechanical polishing is performed until the inter metaldielectric layer 24 is exposed so as to form the plugs 26 and 28 fillingthe via holes V1-V3. After forming the metal layer on the second intermetal dielectric 24, metal wirings 30 are formed for applying voltagesto the first to third electrodes 12, 16, and 20 through the plugs 26 and28.

As described above, the present invention uses the etch stop layer suchthat even though the via holes exposing the respective electrode areformed with differing depths, the surfaces of the respective electrodesare not damaged. Also, since the via holes can be formed in a singleetching process, it is possible to simplify the manufacturing process,resulting in improvement of device reliability and productivity.

Although preferred embodiments of the present invention have beendescribed in detail hereinabove, it should be clearly understood thatmany variations and/or modifications of the basic invention conceptsherein taught which may appear to those skilled in the present art willstill fall within the spirit and scope of the present invention, asdefined in the appended claims.

The present application incorporates by reference in its entirety anapplication entitled CAPACITOR OF SEMICONDUCTOR DEVICE AND FABRICATINGMETHOD THEREOF filed in the Korean Patent Office on Dec. 31, 2004, andassigned serial no. 10-2003-0101822.

1. A capacitor for a semiconductor device, comprising: a first intermetal dielectric layer disposed on a substrate; a first electrodedisposed on the first inter metal dielectric layer; a second electrodepartially overlapping the first electrode; a first dielectric layerdisposed between the first and second electrodes; a third electrodepartially overlapping the second electrode; a second dielectric layerdisposed between the second and third electrodes; an etch stop layerdisposed on the first, second, and third electrodes; a second intermetal dielectric layer formed on the etch stop layer and comprisingfirst, second, and third via holes exposing the first and thirdelectrodes and the etch stop layer; and first, second, and third plugsdisposed in the first, second, and third via holes.
 2. The capacitoraccording to claim 1, wherein the etch stop layer comprises a nitridematerial.
 3. The capacitor according to claim 1, wherein at least one ofthe inter metal dielectric layers comprises an oxide material.
 4. Thecapacitor according to claim 1, wherein a portion of the firstdielectric layer disposed between the first and second electrodes has athickness less than an adjacent portion of the first dielectric layer,and a portion of the second dielectric layer disposed between the secondand third parts has a thickness less than an adjacent portion of thesecond dielectric layer.
 5. The capacitor according to claim 1, whereinthe first electrode, the first dielectric layer, the second electrode,the second dielectric layer, and the third electrode are sequentiallylayered.
 6. The capacitor according to claim 5, wherein the first viahole exposes the second electrode at a position that does not overlapthe first and third electrodes, the second via hole exposes the thirdelectrode, and the third via hole exposes the first electrode at aposition that does not overlap the second and third electrodes.
 7. Amethod for fabricating a capacitor for a semiconductor device,comprising: forming a first inter metal dielectric layer on a substrate;forming a first metal layer to fill a trench on the first inter metaldielectric layer; polishing the first metal layer using a chemicalmechanical polishing to form a first electrode; forming a firstdielectric layer, a second metal layer, a second dielectric layer, and athird metal layer on the first electrode; patterning the third metallayer using a selective etching to form a third electrode; patterningthe second metal layer using the selective etching to form a secondelectrode that overlaps the first electrode and the third electrode;forming an etch stop layer and a second inter metal dielectric layer tocover the first, second, and third electrodes; etching the second intermetal dielectric layer using a selective photolithography process toform via holes to expose the etch stop layer; removing the etch stoplayer to expose the first, second, and third electrodes; filling the viaholes to form plugs, the plugs electric connecting with the first,second, and third electrodes; and forming metal wirings on the secondinter metal dielectric layer to conduct electricity to the first tothird electrodes through the plugs.
 8. The method according to claim 7,wherein the etch stop layer comprises a nitride material.
 9. The methodaccording to claim 7, wherein the inter metal dielectric layer comprisesan oxide material.
 10. A capacitor for a semiconductor device,comprising: a first dielectric layer disposed on a substrate; a firstelectrode disposed on the first dielectric layer; a second electrodepartially overlapping the first electrode; a second dielectric layerdisposed between the first and second electrodes; a third electrodepartially overlapping the second electrode; a third dielectric layerdisposed between the second and third electrodes; an etch stop layerdisposed on the first, second, and third electrodes; a fourth dielectriclayer formed on the etch stop layer and comprising first, second, andthird via holes exposing the first and third electrodes and the etchstop layer; and first, second, and third plugs disposed in the first,second, and third via holes.
 11. The capacitor according to claim 10,wherein the etch stop layer comprises a nitride material.
 12. Thecapacitor according to claim 10, wherein at least one of the dielectriclayer comprises an oxide material.
 13. The capacitor according to claim10, wherein at least one of the first and fourth dielectric layerscomprises an oxide material.
 14. The capacitor according to claim 10,wherein a portion of the second dielectric layer disposed between thefirst and second electrodes has a thickness less than an adjacentportion of the second dielectric layer, and a portion of the thirddielectric layer disposed between the second and third parts has athickness less than an adjacent portion of the third dielectric layer.15. The capacitor according to claim 17, wherein the first via holeexposes the second electrode at a position that does not overlap thefirst and third electrodes, the second via hole exposes the thirdelectrode, and the third via hole exposes the first electrode at aposition that does not overlap the second and third electrodes.
 16. Thecapacitor according to claim 17, wherein at least one of the first andfourth dielectric layers comprises an inter metal dielectric layer. 17.The capacitor according to claim 10, wherein the first electrode, thesecond dielectric layer, the second electrode, the third dielectriclayer, and the third electrode are sequentially layered.